1) Field of the Invention
The invention is in the field of Semiconductor Processing.
2) Description of Related Art
For the past several decades, the scaling of features in integrated circuits has been the driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of logic and memory devices on a microprocessor, lending to the fabrication of products with increased complexity.
Scaling has not been without consequence, however. As the dimensions of the fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the interconnecting wiring between the fundamental building blocks have become overwhelming. For example, metal interconnects are utilized in the fabrication of integrated circuits as a means of connecting various electronic and semiconductor devices into a global circuitry. Two key factors considered when fabricating such metal interconnects are the resistance (R) of each metal interconnect and the coupling capacitance (C), i.e. cross-talk, generated between metal interconnects. Both of these factors hamper the efficiency of metal interconnects. Thus, it has been desirable to reduce both the resistance in and the capacitance between metal interconnects in order to mitigate the so called “RC-delay.”
For the past decade, the performance of integrated circuits, such as those found on microprocessors, has been greatly enhanced by the incorporation of copper interconnects into the “back-end” of line processing scheme. The presence of such copper interconnects, versus aluminum interconnects, greatly reduces the resistance of such interconnects lending to their improved conduction and efficiency.
Attempts to reduce the coupling capacitance generated between metal interconnects have included the use of low-K (K<3.9) dielectric layers that house the metal interconnects, where K is the dielectric constant of the dielectric layers. However, the incorporation of such films has proven to be challenging. For example, processing steps that occur following the deposition of such a low-K dielectric layer may undesirably increase its dielectric constant, lending to increased cross-talk between metal lines.
Thus, a method for restoring low dielectric constant film properties is described herein.